Field of the Invention
Embodiments of the present invention relate generally to accessing and modifying settings of a NAND flash memory device, and particularly to accessing and modifying settings of a NAND flash memory device configured for interconnection via serial peripheral interface.
Description of the Related Art
Generally, most NAND flash memory devices employ parallel communication between a NAND flash device and a host device across a multitude of input pins. Though effective, the quantity of pins vastly increases the amount of space a NAND flash memory device occupies on an integrated circuit (IC) chip. As an alternative to parallel communication, serial communication may reduce the number of interconnections. However, critical functionality may be reduced as the quantity of input pins decreases.
Serial peripheral interface (SPI) permits a synchronous serial data link between a master and one or more slave devices. For a synchronous serial connection to one slave device, SPI uses four wires, including chip select (CS), serial clock (SCK), master out slave in (MOSI, or SI), and master in slave out (MISO, or SO). To communicate with additional slave devices, a unique additional CS wire accompanies each device, though the additional devices may share the same SCK, SI, and SO wires. As slave devices are selected by the master one at a time, only one slave device will communicate with the master at any given moment.
The master typically enables a slave device by setting CS low. Once enabled, the slave device may communicate with the master. With data transmission synchronized to the serial clock signal (SCK), the master initiates the data frame, sending data signals on the slave in (SI) wire and receiving data on the slave out (SO) wire. Because both transmitting and receiving take place simultaneously, SPI communication may be referred to as full duplex.
Devices which have been configured to communicate using SPI include EEPROM and NOR flash memory, two forms of nonvolatile memory devices. SPI EEPROM allows ICs with as few as eight pins, while conventional EEPROM may require 32 pins or more. SPI NOR flash memory similarly allows ICs with substantially fewer pins than conventional NOR memory.
NOR flash memory may be considered well suited to SPI. Because NOR flash memory provides full address and data buses, NOR may offer random access to any memory location. Accordingly, with a serial communication protocol such as SPI, NOR may rather easily output a desired point of data.
On the other hand, NOR flash may generally prove less desirable than other memory formats, such as NAND flash, in many applications. NAND flash memory employs shorter erase times while occupying less die space than NOR flash. Additionally, NAND flash memory cells may endure a greater number of write and erase cycles than NOR flash, often by a factor of ten or more.
Due in part to the nature of NAND memory which reads out page by page, rather than providing random access to any memory location, NAND has been historically considered unfit for use with SPI. Moreover, because much standard NAND functionality depends on enabling various input pins at certain times, attempts to combine the two may require an unwieldy translation from SPI to standard NAND, and/or may fail to provide many useful features that may be desired.
Embodiments of the present invention may be directed to one or more of the problems set forth above.